In ripple carry adders, the carry propagation time is the major speed limiting factor.

Most other arithmetic operations, e.g. multiplication and division are implemented using several add/subtract steps. Thus, improving the speed of addition will improve the speed of all other arithmetic operations.

Accordingly, reducing the carry propagation delay of adders is of great importance. Different logic design approaches have been employed to overcome the carry propagation problem.

One widely used approach employs the principle of carry

**look-ahead****solves this problem by calculating the carry signals in advance, based on the input signals.**This type of adder circuit is called as carry look-ahead adder (CLA

**adder)****.**It is based on the fact that a carry signal will be generated in two cases:**(1)**when both bits A

_{i }and B

_{i }are 1, or

**(2)**when one of the two bits is 1 and the carry-in (carry of the previous stage) is 1.

To understand the carry propagation problem, let’s consider the case of adding two n-bit numbers

**A**and**B**.The Figure shows the full adder circuit used to add the operand bits in the ith

^{ }column; namely A_{i }& B_{i }and the carry bit coming from the previous column (C_{i }).In this circuit, the 2 internal signals P

_{i }and G_{i }are given by: The output sum and carry can be defined as :

**G**is known as the carry Generate

_{i }**signal since a carry (C**

_{i+1}) is generated whenever G

_{i }=1, regardless of the input carry (C

_{i}).

**P**is known as the carry propagate

_{i }**signal since whenever P**

_{i }=1, the input carry is propagated to the output carry, i.e., C

_{i+1}. = C

_{i }(note that whenever P

_{i }=1, G

_{i }=0).

Computing the values of P

_{i }and G_{i }only depend on the input operand bits (A_{i }& B_{i}) as clear from the Figure and equations.Thus, these signals settle to their steady-state value

**after the propagation through their respective gates.**Computed values of all

**the P**_{i}’s are valid one XOR-gate delay after the operands A and B are made valid.Computed values of all

**the G**_{i}’s are valid one AND-gate delay after the operands A and B are made valid.The Boolean expression of the carry outputs of various stages can be written as follows:

**C**

_{1 }= G_{0 }+ P_{0}C_{0 }**C**

_{2 }= G_{1 }+ P_{1}C_{1 }= G_{1 }+ P_{1 }(G_{0 }+ P_{0}C_{0})**= G**

_{1 }+ P_{1}G_{0 }+ P_{1}P_{0}C_{0 }**C**

_{3 }= G_{2 }+ P_{2}C_{2 }= G_{2 }+ P_{2}G_{1 }+ P_{2}P_{1}G_{0 }+ P_{2}P_{1}P_{0}C_{0 }**C**

_{4 }= G_{3 }+ P_{3}C_{3 }**= G**

_{3 }+ P_{3}G_{2 }+ P_{3}P_{2}G_{1 }+ P_{3}P_{2}P_{1}G_{0 }+ P_{3}P_{2}P_{1}P_{0}C_{0 }In general, the ith

^{ }carry output is expressed in the form**C****= F**_{i }_{i }(P’s, G’s ,**C**)._{0}In other words, each carry signal is expressed as a direct SOP function of

**C**rather than its preceding carry signal._{0 }Since the Boolean expression for each output carry is expressed in SOP form, it can be implemented in two-level circuits.

The 2-level implementation of the carry signals has a propagation delay of 2 gates, i.e., 2τ.

The 4-bit carry look-ahead (CLA) adder consists of 3 levels of logic:

**First level:**Generates all the P & G signals. Four sets of P & G logic (each consists of an XOR gate and an AND gate). Output signals of this level (P’s & G’s) will be valid after 1τ.

**Second level:**The Carry Look-Ahead (CLA) logic block which consists of four 2-level implementation logic circuits. It generates the carry signals (C

_{1}, C

_{2}, C

_{3}, and C

_{4}) as defined by the above expressions. Output signals of this level (C

_{1}, C

_{2}, C

_{3}, and C

_{4}) will be valid after 3τ.

**Third level:**Four XOR gates which generate the sum signals (S

_{i}) (S

_{i }= P

_{i }⊕ C

_{i}). Output signals of this level (S

_{0}, S

_{1}, S

_{2}, and S

_{3}) will be valid after 4τ.

Thus, the 4 Sum signals (S

_{0}, S_{1}, S_{2 }& S_{3}) will all be valid after a total delay of 4τ compared to a delay of (2n+1)τ for Ripple Carry adders.For a 4-bit adder (n = 4), the Ripple Carry adder delay is 9τ.

The disadvantage of the CLA adders is that the carry expressions (and hence logic) become quite complex for more than 4 bits.

This is really a good site with great information along with excellent post for all to view and comment on this site.The information present here is helpful for the readers.Overall wonderful site.

ReplyDeleteI think you’ve made some truly interesting points. Not too many people would actually think about this the way you just did. I am really impressed that there is so much information about this subject that have been uncovered and you did it so well, with so much class. Thanks.

ReplyDelete