Previously we have discussed about multiplexer circuit, decorder, encoder, half adder, full adder, half subtractor, full subtractor and universal gate. Now let we try to discuss about something else. So in this topic we will try to discuss about Combinational Logic Implementation. To write more specifically we will discuss about the implementation of a full adder circuit with a decorder and two OR Gates.

To do this at first we need to review the truth table of Full Adder circuit.

Inputs a b c | Outputs C S |

0 0 0 | 0 0 |

0 0 1 | 0 1 |

0 1 0 | 0 1 |

0 1 1 | 1 0 |

1 0 0 | 0 1 |

1 0 1 | 1 0 |

1 1 0 | 1 0 |

1 1 1 | 1 1 |

Fig: Truth table of Full Adder Circuit

From the truth table we have been found that

S(a,b,c)=sum(1,2,4,7)

C(a,b,c)=sum(3,5,6,7)

As there are three inputs and eight min-terms, so have to use 3 to 8 line decorder. The generates the eight min-terms for a, b, c.

The OR Gate for output S forms the sum of min-terms 1, 2, 4 and 7. The OR Gate output C forms the sum of min-terms 3, 5, 6 and 7.

Circuit Diagram

A function with a long list of min-terms requires an OR Gate with a large number of inputs. A function F having a list of K min-terms can be expressed in its complemented form F’ with 2^n-K min-terms. If the number of min-terms in a function is greater than 2^n/2, then F’ can be expressed with fewer min-terms than required for F. In such a case, it is suitable to use a NOR Gate to sum the min-terms of F’. The output of the NOR Gate will generate the normal output F.

The decorder method can be used to implement any combinational circuit. It is necessary to implementing with comparing to all other possible implementations to determine the solution.

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